1. Field of the Invention
The present invention relates to a matrix for switching between two groups of multiplexes of several input and output channels, respectively. A multiplex, as understood in the invention, is a time-division multiplex transmission (TDM).
2. Discussion of the Related Art
In such a time-division multiplex transmission, a multiplex frame is divided in time slots TS, for example thirty-two, and each time slot includes a determined number of bits, for example eight. To transmit a given channel, it is assigned one or several time slots TS according to the desired rate.
In an application to telephony, or to transmitting digital data via the telephone network, the duration of a multiplex frame of thirty-two time slots TS is standardized to 125 microseconds and each time slot TS includes eight bits. The global rate of such a multiplex is 2.048 Mbits/s and the rate of a given time slot TS is 64 Kbits/s.
Several communications are generally carried by such a multiplex. The function of a switch matrix is then to direct the different incoming communications carried by several incoming multiplexes, for example eight, to a same number of outgoing multiplexes, for example within a telephone switch center, to ensure the connection between two subscribers, whether for a transmission of voice or digital data. In the case of voice, it can be sampled and transmitted by the switch matrix.
Reference will be made hereunder to a matrix for switching between eight incoming multiplexes and eight outgoing multiplexes, each multiplex being constituted by thirty-two time slots, each including eight bits.
FIG. 1 illustrates an example of embodiment of a conventional switch matrix 1 operating strictly without contention for transmissions at a maximum rate of 64 Kbits/s.
Matrix 1 includes eight input junctions JE.sub.0 to JE.sub.7 and eight output junctions JS.sub.0 to JS.sub.7. Each of the incoming multiplexes arrives onto an input junction JE.sub.k and each of the eight outgoing multiplexes is supplied by an output junction JS.sub.l.
Each time slot TS is identified within matrix 1 by an 8-bit address. Three bits of this address identify the number of the multiplex, or of the junction, while five bits identify the number of the time slot TS in the frame of the multiplex considered.
For bidirectional communications, for example voice, a same subscriber is assigned a time slot ITS.sub.i of an incoming multiplex as well as a time slot OTS.sub.j of an outgoing multiplex. These time slots are carried over input and output junctions, or multiplexes, JE.sub.k and JS.sub.l, respectively. Assuming that an incoming multiplex is connected to junction JE.sub.0 and that the time slot ITS.sub.4 of this multiplex is assigned to a subscriber M during a bidirectional communication, the time slot OTS.sub.4 of the outgoing multiplex connected to junction JS.sub.0 is also assigned to this subscriber M.
A switch matrix is said to be strictly contentionless if, when a subscriber M desires to communicate with a subscriber N and the latter is available, the matrix links the two subscribers with no further condition.
FIG. 2 illustrates a conventional example of implementation of a switch matrix such as shown in FIG. 1.
Matrix 1 is implemented by means of two memories of 256 8-bit words. An assignment memory 2 is meant to contain the paths of the different transmissions, that is, the time slot ITS.sub.i of an incoming multiplex associated, for a given communication, with a time slot OTS.sub.j of an outgoing multiplex. A memory 3 is meant to store the eight bits of each time slot ITS.sub.i relative to the different transmissions arriving in multiplex at junctions JE.sub.0 to JE.sub.7 so that they can be directed towards junctions JS.sub.0 to JS.sub.7 depending on the destinations.
Memory 3 receives, via a series-to-parallel converter 4, the data (the eight bits of each time slot ITS.sub.i) arriving at junctions JE.sub.0 to JE.sub.7. It issues them, via a parallel-to-series converter 5, to junctions JS.sub.0 to JS.sub.7. The addressing of memory 3 is performed by identifying the incoming time slots ITS.sub.i. In other words, the 8-bit address includes the number i of the time slot ITS.sub.i on five most significant bits and the number k of the input junction JE.sub.k on the three least significant bits.
The address input A of memory 3 is connected to the output of a two-input first multiplexer 6 having the function of issuing, for each bit cycle, a write address and a read address. In other words, the selection of the input of multiplexer 6 changes for each half-bit cycle and is, for example, controlled by a bit clock HB at the bit rate in the frames of the multiplex. Thus, for each bit cycle, an 8-bit word, corresponding to the contents of a time slot ITS.sub.i of an incoming multiplex and issued by converter 4 to a data input D.sub.I of memory 3, is written into the latter, and an 8-bit word, corresponding to the contents of a time slot OTS.sub.j of an outgoing multiplex, is issued on a data output D.sub.O of memory 3 for converter 5. The duration of a write or read cycle of memory 3 is, at most, one half-bit cycle.
The write address in memory 3 is supplied by a first 8-bit counter 7 incremented at the rate of bit clock HB (for example 2.048 MHz) and synchronized at the beginning of each multiplex frame. Counter 7 is not reset by frame synchronization signal FS but is initialized according to the time .tau..sub.e required for the paralleling by converter 4. The initialization value is selected so that, when counter 7 is at zero, the eight bits present at data input D.sub.I of memory 3 correspond to the first time slot ITS.sub.0 of the first incoming multiplex at input junction JE.sub.0. This time generally corresponds, in practice, to eight bit cycles.
The read address of memory 3 is supplied by memory 2. In other words, the data words at the output D.sub.O of memory 2 constitute the read addresses of memory 3. The duration of a write or read cycle of memory 2 is, as for memory 3, at most one half-bit cycle. The addressing of memory 2 is performed by identifying the outgoing time slots OTS.sub.j. In other words, the 8-bit address includes the number j of the outgoing time slot OTS.sub.j on five most significant bits and the number l of output junction JS.sub.l on three least significant bits.
The address input A of memory 2 is connected to the output of a second two-input multiplexer 8. A first input receives an address issued by a microprocessor .mu.P (not shown) and a second input receives an address issued by a second counter 9 over eight bits.
The selection of the input of multiplexer 8 is performed by the microprocessor to enable it, at the beginning of a new communication, to indicate the path of this communication. At the beginning of each new communication, the microprocessor addresses memory 2 according to the subscriber who is the receiver and writes into this memory the address of the sending subscriber. For a bidirectional communication, the microprocessor must perform two write cycles at the beginning of each new communication.
The reading of memory 2 is cyclic. It is performed according to the addresses of the receiver subscribers, that is, according to the time slots OTS.sub.j of the outgoing multiplexes, by means of counter 9. This counter 9 is, like counter 7, incremented by bit clock HB and synchronized at each frame start. Like counter 7, counter 9 is not reset by frame synchronization signal FS. It is initialized according to the time .tau..sub.S required for the serializing by converter 5, which generally corresponds, in practice, to eight bit cycles. The initialization value is selected such that, when counter 9 is at zero, the bit present on each output junction JS.sub.0 to JS.sub.7 corresponds to the first bit of the first time slot ITS.sub.0 of each incoming multiplex.
Since memories 2 and 3 are read at the rate of bit clock HB, counters 7 and 9 are actually phase shifted by seventeen bit cycles (eight bit cycles for each converter and one bit cycle for memory 3). This phase shift corresponds to the minimum propagation duration through matrix 1, counter 9 being in phase advance with respect to counter 7. The incoming and outgoing multiplexes are thus synchronized on the same frame synchronization signal FS.
For clarity, not all the signals and clock links have been shown. Particularly, converters 4 and 5 also operate at the rate of bit clock HB.
Even though such a matrix enables a strict contentionless operation for transmissions with a rate not exceeding 64 Kbits/s, it cannot be used for multiplex frames wherein several time slots TS are assigned to a same transmission channel.
Indeed, as soon as a transmission has to occupy several time slots TS of a multiplex, for example two for a transmission at 128 Kbits/s, such a matrix cannot respect the integrity of the sequence of the transmission while being strictly contentionless.
Actually, since counters 7 and 9 are phase shifted by seventeen bit cycles, the integrity of the sequences can only be respected if the microprocessor ensures that the time slots OTS.sub.j of an output junction JS.sub.l assigned to a given transmission channel are distant by at least three time slots TS from the time slots ITS.sub.i constituting the transmission channel on input junction JE.sub.k. The microprocessor further has to ensure that the time slots, respectively ITS.sub.i and OTS.sub.j, are in the same order at the input and output junctions JE.sub.k and JS.sub.l, respectively. Matrix 1 is then no longer strictly contentionless.
FIG. 3 illustrates an example of unidirectional communication from a subscriber M to a subscriber N over a channel at 128 Kbits/s, constituted by two time slots TS of a same multiplex.
Subscriber M is, for example, assigned time slots ITS.sub.4 and ITS.sub.20 of input junction JE.sub.0 and subscriber N is, for example, assigned time slots OTS.sub.10 and OTS.sub.21 of output junction JS.sub.3.
FIG. 3 shows, in the form of timing diagrams, the states of counters 7 and 9, the contents of the incoming and outgoing time slots, respectively ITS.sub.4 and ITS.sub.20, and OTS.sub.10 and OTS.sub.21, assigned to this communication on input and output junctions JE.sub.0 and JS.sub.3, respectively, and the addresses (ITS.sub.4, JE.sub.0) and (ITS.sub.20, JE.sub.0) of memory 3. The write and read times of memory 3 have been shown by arrows in dotted lines.
For clarity, the timing diagrams of FIG. 3 are not to scale and the half-bit cycle shift between the write and read cycles occurring in a same bit cycle has not been shown.
Since the minimum time of propagation across matrix 1 is seventeen bit cycles, all the 8-bit words contained in the time slots ITS.sub.20 of junction JE.sub.0 are transferred into the time slots OTS.sub.21 of junction JS.sub.3, but with a delay of one frame with respect to the words contained in the time slots ITS.sub.4 of junction JE.sub.0 which are transferred into the time slots OTS.sub.10 of junction JS.sub.3.
A message transmitted by subscriber M for example in a sequence UVWXYZ, where each letter stands for an 8-bit word and assuming that this message constitutes a whole sequence preceded by a word "T" and followed by a word "A", will become, on output junction JS.sub.3, UTWVYXAZ.
Indeed, the writing of the words "U", "W" and "Y" is performed in three successive frames at the address (ITS.sub.4, JE.sub.0) of memory 3, upon the appearance of count 00100 000 (ITS.sub.4, JE.sub.0) in counter 7. The writing of the words "V", "X" and "z" is performed, in three successive frames at the address (ITS.sub.20, JE.sub.0) of memory 3, upon the appearance of count 10100 000 (ITS.sub.20, JE.sub.0) in counter 7.
The reading of each word "U", "W" and "Y" is performed, during the frame wherein it has been written, upon the appearance of count 01010 011 (OTS.sub.10, JS.sub.3) in counter 9 which addresses memory 2 so that it issues the read address 00100 000 (ITS.sub.4, JE.sub.0) of memory 3.
Conversely, the reading of each word "V", "X" and "Z" is performed, during the frame which follows that wherein it has been written, upon the appearance of count 10101 011 (OTS.sub.21, JS.sub.3) in counter 9 which addresses memory 2 so that it issues the read address 10100 000 (ITS.sub.20, JE.sub.0) of memory 3. Indeed, the seventeen bit cycle advance of counter 9 with respect to counter 7 results in count 10101 011 appearing in counter 9 before count 10100 000 appears in counter 7.
The offset between time slots ITS.sub.4 and ITS.sub.20 of input junction JE.sub.0 and the counts, respectively 00100 000 and 10100 000 in counter 7, corresponds to the time .tau..sub.e for paralleling the data by converter 4. Similarly, the offset between the appearance of counts 01010 011 and 10101 011 in counter 9 and the time slots, respectively OTS.sub.10 and OTS.sub.21 of junction JS.sub.3, corresponds to the time .tau..sub.S for serializing the data by converter 5.